Semiconductor equipment 100 having a plurality of semiconductor devices 101 and upper and lower layer wirings according to a prior art is disclosed in Japanese Unexamined Patent Application Publication No. H07-263665. As shown in FIG. 13, the semiconductor equipment 100 includes a plurality of laterally diffused metal oxide semiconductor (i.e., L-DMOS) transistors 101 having a source cell S and a drain cell D. The L-DMOS transistors 101 are arranged to have a mesh pattern. The first wiring layer as the lower layer wiring is formed on the source and drain cells S, D through the first interlayer insulation film. Further, the second wiring layer as the upper layer wiring is formed on the first wiring layer through the second interlayer insulation film.
The lower layer wiring is composed of a plurality of the first source wirings 1 and a plurality of the first drain wirings 2. Each first source wiring 1 connects to a plurality of the source cells S, which are aligned in a diagonal direction of the mesh pattern. Each first drain wiring 2 connects to a plurality of the drain cells D, which are also aligned in the diagonal direction. The first source wirings 1 and the first drain wirings 2 are aligned alternately. The upper layer wiring is composed of the second source wiring 3 and the second drain wiring 4. The second source wiring 3 connects to a plurality of first source wirings 1 through contact portions (not shown) disposed under the second source wiring 3, and the second drain wiring 4 connects to a plurality of first drain wirings 2 through contact portions (not shown) disposed under the second drain wiring 4. The second source wiring 3 and the second drain wiring 4 almost equally divide the semiconductor equipment 100, and each of them has a triangle shape.
Since the wirings for connecting each cell in the L-DMOS transistor 101 are formed into double layered structure, i.e., formed into the upper and lower layer wirings, so that an occupation area of the upper and lower layer wirings is reduced. Moreover, each cell can be minimized, so that a chip size of the semiconductor equipment 100 is reduced.
Each of the second source and drain wirings 3, 4 as the upper layer wiring has a wide area so that the electric resistance of the upper layer wiring as a wiring resistance is suppressed. Further, each wide area of the upper layer wiring can be used as a pad region for forming a solder bump. Therefore, the semiconductor equipment 100 can be mounted on a ceramic circuit board or a printed circuit board so that the semiconductor equipment 100 is packaged into a chip size package (i.e., CSP). Therefore, a mounting area of the semiconductor equipment 100 is reduced.
However, each of the source and drain cells S, D connecting to the lower layer wirings is affected by the wiring resistance differently. For example, a source cell B shown in FIG. 13, which is disposed under the second source wiring 3, connects to the second source wiring 3 at a right above contact portion. Therefore, the source cell B is not affected by the wiring resistance of the first source wiring 1 substantially. A source cell C shown in FIG. 13 is disposed under the second drain wiring 4, i.e., the source cell C is not disposed under the second source wiring 3. Therefore, the source cell C is far from a contact portion between the first source wiring 1 and the second source wiring 3, so that the source cell C is much affected by the wiring resistance of the first source wiring 1. In other words, current flowing from the source cell C passes through the first source wiring 1, which is narrow and has a long path.
The above different affection of the wiring resistance breaks down the balance of current flowing through each cell. For example, the current concentrates on the source cell B, and the current does not flow through the source cell C substantially, so that the total withstand voltage of the semiconductor equipment 100 is reduced.